TMS320VC549 datasheet(26/60 Pages) TI

26 / 60 page

TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a parallel I/O port write

(IOSTRB = 0) [H = 0.5 tc(CO)] (see Figure 8)†

PARAMETER

’549-80

’549-100

’549-120

UNIT

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

td(CLKL-A)

Delay time, address valid from CLKOUT low‡

– 1

td(CLKH-ISTRBL)

Delay time, IOSTRB low from CLKOUT high

td(CLKH-D)IOW

Delay time, write data valid from CLKOUT high

H–5

H+7

H–5

H+7

H–5

H+6

td(CLKH-ISTRBH)

Delay time, IOSTRB high from CLKOUT high

– 1

td(CLKL-RWL)

Delay time, R/W low from CLKOUT low

td(CLKL-RWH)

Delay time, R/W high from CLKOUT low

th(A)IOW

Hold time, address valid from CLKOUT low‡

– 1

th(D)IOW

Hold time, write data after IOSTRB high

H–4

H+4

H–3

H+3

H–3

H+3

tsu(D)IOSTRBH

Setup time, write data before IOSTRB high

H–5

H+1

H–5

H+1

H–5

tsu(A)IOSTRBL

Setup time, address valid before IOSTRB low

H–5

H+5

H–3

H+3

H–3

H+3

† See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.

‡ Address and IS timings are included in timings referenced as address.

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