TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

41

POST OFFICE BOX 1443

serial port receive timing

(see Figure 21)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

tc(SCK)

Cycle time, serial port clock

6H

†

ns

tf(SCK)

Fall time, serial port clock

6

ns

tr(SCK)

Rise time, serial port clock

6

ns

tw(SCK)

Pulse duration, serial port clock low/high

3H

ns

tsu(FSR)

Setup time, FSR before CLKR falling edge

4

ns

th(FSR)

Hold time, FSR after CLKR falling edge

4

ns

th(DR)

Hold time, DR after CLKR falling edge

6

ns

tsu(DR)

Setup time, DR before CLKR falling edge

6

ns

† The serial port design is fully static and, therefore, can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.

BIT

DR

FSR

CLKR

8/16

7/15

2

1

tsu(DR)

tsu(FSR)

th(FSR)

tw(SCK)

tr(SCK)

tf(SCK)

tw(SCK)

th(DR)

tc(SCK)

Figure 21. Serial Port Receive Timing