TMS320VC549 datasheet(22/60 Pages) TI

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TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a memory write

(MSTRB = 0) [H = 0.5 tc(CO)]†‡ (see Figure 6)

PARAMETER

’549-80

’549-100

’549-120

UNIT

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

td(CLKH-A)

Delay time, address valid from CLKOUT high§

– 1

td(CLKL-A)

Delay time, address valid from CLKOUT low¶

– 1

td(CLKL-MSL)

Delay time, MSTRB low from CLKOUT low

– 1

td(CLKL-D)W

Delay time, data valid from CLKOUT low

td(CLKL-MSH)

Delay time, MSTRB high from CLKOUT low

– 1

td(CLKH-RWL)

Delay time, R/W low from CLKOUT high

– 1

td(CLKH-RWH)

Delay time, R/W high from CLKOUT high

– 1

td(RWL-MSTRBL)

Delay time, MSTRB low after R/W low

H – 2

H + 3

H – 2

H + 2

H – 2

H + 2

th(A)W

Hold time, address valid after CLKOUT high§

– 1

th(D)MSH

Hold time, write data valid after MSTRB high

H–4

H+4¶

H–3

H+3¶

H–3

H+3¶

tw(SL)MS

Pulse duration, MSTRB low

2H–5

2H–4

tsu(A)W

Setup time, address valid before MSTRB low

2H–5

2H–4

tsu(D)MSH

Setup time, write data valid before MSTRB high

2H–7

2H+7¶

2H–5

2H+5¶

2H–4

2H+4¶

† Address, PS, and DS timings are all included in timings referenced as address.

‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.

§ In the case of a memory write preceded by a memory write.

¶ In the case of a memory write preceded by an I/O cycle.

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