TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

48

POST OFFICE BOX 1443

serial-port receive timing in TDM mode

timing requirements over recommended ranges of supply voltage and operating free-air

’549-80

’549-100

’549-120

UNIT

MIN

MAX

tc(SCK)

Cycle time, serial-port clock

16H

†

ns

tf(SCK)

Fall time, serial-port clock

6

ns

tr(SCK)

Rise time, serial-port clock

6

ns

tw(SCK)

Pulse duration, serial-port clock low/high

8H

ns

tsu(TD-TCH)

Setup time, TDAT/TADD before TCLK rising edge

10

ns

th(TCH-TD)

Hold time, TDAT/TADD after TCLK rising edge

1

ns

tsu(TF-TCH)

Setup time, TFRM before TCLK rising edge‡

10

ns

th(TCH-TF)

Hold time, TFRM after TCLK rising edge‡

10

ns

† The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching infinity. It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.

‡ TFRM timing and waveforms shown in Figure 27 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is

illustrated in the transmit timing diagram in Figure 28.