TMS320VC549 datasheet(53/60 Pages) TI

53 / 60 page

TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

host port interface timing (continued)

timing requirements over recommended operating conditions [H = 0.5tc(CO)] (see Note 7)

(see Figure 29 through Figure 32)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

MIN

MAX

UNIT

tsu(HBV-DSL)

Setup time, HAD/HBIL valid before DS or HAS falling edge

th(DSL-HBV)

Hold time, HAD/HBIL valid after DS or HAS falling edge

tsu(HSL-DSL)

Setup time, HAS low before DS falling edge

tw(DSL)

Pulse duration, DS low

tw(DSH)

Pulse duration, DS high

Cycle time, DS rising

Case 1: HOM access timings

(see Access Timing Without HRDY)

tc(DSH-DSH)

Cycle time, DS rising

edge to next DS rising

edge

Case 2a: SAM accesses and HOM active writes

to DSPINT or HINT†

(see Access Timings With HRDY)

10H

tsu(HDV-DSH)

Setup time, HD valid before DS rising edge

td(DSH-HSL)‡

Delay time, DS high to next HAS low

10H

th(DSH – HDV)W

Hold time, HD valid after DS rising edge, write

† A host not using HRDY should meet this timing requirement all the time unless a software handshake is used to change the access rate according

to the HPI mode.

‡ Must only be met if HAS is going low when not accessing the HPI (as would be the case where multiple devices are being driven by one host).

NOTE 7: SAM = shared-access mode, HOM = host-only mode

HAD stands for HCNTRL0, HCNTRL1, and HR/W.

HDS refers to either HDS1 or HDS2.

DS refers to the logical OR of HCS and HDS.

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