TMS320VC549 datasheet(35/60 Pages) TI

номер детали	TMS320VC549

подробное описание детали	FIXED-POINT DIGITAL SIGNAL PROCESSOR

PDF	60 Pages

Scroll/Zoom	100%

производитель	TI [Texas Instruments]

домашняя страница	http://www.ti.com

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35 / 60 page

TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

HOLD and HOLDA timing

switching characteristics over recommended operating conditions for memory control signals

and HOLDA [H = 0.5 tc(CO)] (see Figure 14)

PARAMETER

’549-80

’549-100

’549-120

UNIT

MIN

MAX

tdis(CLKL-A)

Disable time, CLKOUT low to address, PS, DS, IS high impedance

tdis(CLKL-RW)

Disable time, CLKOUT low to R/W high impedance

tdis(CLKL-S)

Disable time, CLKOUT low to MSTRB, IOSTRB high

impedance

ten(CLKL-A)

Enable time, CLKOUT low to address, PS, DS, IS

2H+5

ten(CLKL-RW)

Enable time, CLKOUT low to R/W enabled

2H+5

ten(CLKL-S)

Enable time, CLKOUT low to MSTRB, IOSTRB enabled

2H+5

Valid time, HOLDA low after CLKOUT low

tv(HOLDA)

Valid time, HOLDA high after CLKOUT low

tw(HOLDA)

Pulse duration, HOLDA low duration

2H–3

timing requirements for HOLD [H = 0.5 tc(CO)] (see Figure 14)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

tw(HOLD)

Pulse duration, HOLD low duration

4H+10

tsu(HOLD)

Setup time, HOLD before CLKOUT low

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