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TMS320VC549 датащи(PDF) 17 Page - Texas Instruments |
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TMS320VC549 датащи(HTML) 17 Page - Texas Instruments |
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17 / 60 page ![]() TMS320VC549 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000 17 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multiply-by-N clock option – PLL enabled The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate the internal machine cycle. When an external clock source is used, the frequency injected must conform to specifications listed in the timing requirements table. switching characteristics over recommended operating conditions for multiply-by-N clock option – PLL enabled [H = 0.5tc(CO)] (see Figure 2 and Figure 4, and the recommended operating conditions table) PARAMETER ’549-80 ’549-100 ’549-120 UNIT PARAMETER MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT tc(CO) Cycle time, CLKOUT 12.5 tc(CI)/N 10 tc(CI)/N 8.33 tc(CI)/N ns td(CIH-CO) Delay time, X2/CLKIN high/low to CLKOUT high/low 3 6 10 3 6 10 3 6 10 ns tf(CO) Fall time, CLKOUT 2 2 2 ns tr(CO) Rise time, CLKOUT 2 2 2 ns tw(COL) Pulse duration, CLKOUT low H–3 H–1 H H–2 H–1 H H–2 H–1 H ns tw(COH) Pulse duration, CLKOUT high H–3 H–1 H H–2 H–1 H H–2 H–1 H ns tp Transitory phase, PLL lock-up time 29 35 45 ms |
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