TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

42

POST OFFICE BOX 1443

serial port transmit timing

switching characteristics over recommended operating conditions for serial port transmit with

PARAMETER

’549-80

’549-100

’549-120

UNIT

MIN

MAX

td(DX)

Delay time, DX valid after CLKX rising

25

ns

th(DX)

Hold time, DX valid after CLKX rising

– 5

ns

tdis(DX)

Disable time, DX after CLKX rising

40

ns

timing requirements over recommended operating conditions for serial port transmit with external

’549-80

’549-100

’549-120

UNIT

MIN

MAX

tc(SCK)

Cycle time, serial port clock

6H

†

ns

th(FSX)

Hold time, FSX after CLKX falling edge (see Note 1)

6

ns

th(FSX)H Hold time, FSX after CLKX rising edge (see Note 1)

2H–3‡

ns

td(FSX)

Delay time, FSX after CLKX rising edge

2H–3

ns

tf(SCK)

Fall time, serial port clock

6

ns

tr(SCK)

Rise time, serial port clock

6

ns

tw(SCK)

Pulse duration, serial port clock low/high

3H

ns

† The serial port design is fully static and, therefore, can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.

‡ If the FSX pulse does not meet this specification, the first bit of serial data is driven on DX until the falling edge of FSX. After the falling edge of

FSX, data is shifted out on DX pin. The transmit buffer-empty interrupt is generated when the th(FSX) and th(FSX)H specification is met.

NOTE 1: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on

the source of FSX, and CLKX timings always are dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX

is independent of the source of CLKX.

DX BIT

FSX

CLKX

8/16

7/15

2

1

th(DX)

td(DX)

tw(SCK)

tw(SCK)

tc(SCK)

td(FSX)

th(FSX)H

th(FSX)

tdis(DX)

tr(SCK)

tf(SCK)

Figure 22. Serial Port Transmit Timing With External Clocks and Frames