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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC549 датащи(PDF) 24 Page - Texas Instruments |
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TMS320VC549 датащи(HTML) 24 Page - Texas Instruments |
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24 / 60 page  TMS320VC549 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory and parallel I/O interface timing (continued) switching characteristics over recommended operating conditions for a parallel I/O port read (IOSTRB = 0)†‡ (see Figure 7) PARAMETER ’549-80 ’549-100 ’549-120 UNIT PARAMETER MIN MAX MIN MAX MIN MAX UNIT td(CLKL-A) Delay time, address valid from CLKOUT low – 1 5 – 1 4 – 1 4 ns td(CLKH-ISTRBL) Delay time, IOSTRB low from CLKOUT high 0 5 0 4 0 4 ns td(CLKH-ISTRBH) Delay time, IOSTRB high from CLKOUT high – 1 5 – 1 4 – 1 4 ns th(A)IOR Hold time, address after CLKOUT low – 1 5 – 1 4 – 1 4 ns † Address and IS timings are included in timings referenced as address. ‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance. |
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