TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

44

POST OFFICE BOX 1443

buffered serial port receive timing

timing requirements over recommended operating conditions (see Figure 24)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

tc(SCK)

Cycle time, serial port clock

20

†

ns

tf(SCK)

Fall time, serial port clock

4

ns

tr(SCK)

Rise time, serial port clock

4

ns

tw(SCK)

Pulse duration, serial port clock low/high

6

ns

tsu(BFSR)

Setup time, BFSR before BCLKR falling edge (see Note 2)

2

ns

th(BFSR)

Hold time, BFSR after BCLKR falling edge (see Note 2)

7

tc(SCK)–2‡

ns

tsu(BDR)

Setup time, BDR before BCLKR falling edge

0

ns

th(BDR)

Hold time, BDR after BCLKR falling edge

7

ns

† The serial port design is fully static and therefore can operate with tc(SCK) approaching infinity. It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.

‡ First bit is read when BFSR is sampled low by BCLKR clock.

NOTE 2: Timings for BCLKR and BFSR are given with polarity bits (BCLKP and BFSP) set to 0.

BCLKR

BFSR

BDR

1

2

8/10/12/16

tr(SCK)

tf(SCK)

Figure 24. Buffered Serial Port Receive Timing