PROASIC3E datasheet(6/37 Pages) ACTEL

6 / 37 page

I/O Structures in IGLOOe and ProASIC3E Devices

6v1.4

Features Supported on Every I/O

Table 6 lists all features supported by transmitter/receiver for single-ended and differential I/Os.

Table 7 on page 7 lists the performance of each I/O technology.

Table 6 • IGLOOe and ProASIC3E I/O Features

Feature

Description

All I/O

•

High performance (Table 7 on page 7)

•

Electrostatic discharge protection

•

I/O register combining option

Single-Ended

and

Voltage-Referenced

Transmitter Features

•

Hot-swap in every mode except PCI or 5 V–input–tolerant (these

modes use clamp diodes and do not allow hot-swap)

•

Activation of hot-insertion (disabling the clamp diode) is

selectable by I/Os.

•

Output slew rate: 2 slew rates

•

Weak pull-up and pull-down resistors

•

Output drive: 5 drive strengths

•

Programmable output loading

•

Skew between output buffer enable/disable time: 2 ns delay on

rising edge and 0 ns delay on falling edge (see "Selectable Skew

between Output Buffer Enable and Disable Times" section on

page 24 for more information)

•

LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs

Single-Ended Receiver Features

•

5 V–input–tolerant receiver (Table 13 on page 19)

•

Schmitt trigger option

•

Programmable delay: 0 ns if bypassed, 0.625 ns with '000'

setting, 6.575 ns with '111' setting, 0.85-ns intermediate delay

increments (at 25°C, 1.5 V)

•

Separate ground plane for GNDQ pin and power plane for VMV

pin are used for input buffer to reduce output-induced noise.

Voltage-Referenced Differential Receiver

Features

•

Programmable delay: 0 ns if bypassed, 0.46 ns with '000' setting,

4.66 ns with '111' setting, 0.6-ns intermediate delay increments

(at 25°C, 1.5 V)

•

Separate ground plane for GNDQ pin and power plane for VMV

pin are used for input buffer to reduce output-induced noise.

CMOS-Style LVDS, B-LVDS, M-LVDS, or

LVPECL Transmitter

•

Two I/Os and external resistors are used to provide a CMOS-style

LVDS, DDR LVDS, B-LVDS, and M-LVDS/LVPECL transmitter

solution.

•

Activation of hot-insertion (disabling the clamp diode) is

selectable by I/Os.

•

High slew rate

•

Weak pull-up and pull-down resistors

•

Programmable output loading

LVDS,

DDR

LVDS,

B-LVDS,

and

M-LVDS/LVPECL

Differential

Receiver

Features

•

Programmable delay: 0 ns if bypassed, 0.46 ns with '000' setting,

4.66 ns with '111' setting, 0.6-ns intermediate delay increments

(at 25°C, 1.5 V)

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