PROASIC3E datasheet(28/37 Pages) ACTEL

28 / 37 page

I/O Structures in IGLOOe and ProASIC3E Devices

v1.4

The slew rate can be implemented by using a PDC command (Table 6 on page 6), setting it "High"

or "Low" in the I/O Attribute Editor in Designer, or instantiating a special I/O macro. The default

slew rate value is "High."

IGLOOe and ProASIC3E devices support output slew rate control: high and low. Actel recommends

the high slew rate option to minimize the propagation delay. This high-speed option may

introduce noise into the system if appropriate signal integrity measures are not adopted. Selecting

a low slew rate reduces this kind of noise but adds some delays in the system. Low slew rate is

recommended when bus transients are expected.

Output Drive

The output buffers of IGLOOe and ProASIC3E devices can provide multiple drive strengths to meet

signal integrity requirements. The LVTTL and LVCMOS (except 1.2 V LVCMOS) standards have

selectable drive strengths. Other standards have a preset value.

Drive strength should also be selected according to the design requirements and noise immunity of

the system.

The output slew rate and multiple drive strength controls are available in LVTTL/LVCMOS 3.3 V,

LVCMOS 2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V, and LVCMOS 1.5 V. All other I/O

standards have a high output slew rate by default.

For other IGLOOe and ProASIC3E devices, refer to Table 15 for more information about the slew

rate and drive strength specification.

There will be a difference in timing between the Standard Plus I/O banks and the Advanced I/O

banks. Refer to the I/O timing tables in the datasheet for the standards supported by each device.

Table 15 • IGLOOe and ProASIC3E I/O Standards—Output Drive and Slew Rate

I/O Standards

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

Slew

LVTTL/LVCMOS 3.3 V

✓✓

✓

✓✓

✓

High

Low

LVCMOS 2.5 V

✓✓

✓

✓✓

✓

High

Low

LVCMOS 2.5/5.0 V

✓✓

✓

✓✓

✓

High

Low

LVCMOS 1.8 V

✓✓

✓

✓✓

–High

Low

LVCMOS 1.5 V

✓✓

✓

–

High

Low

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