I/O Structures in IGLOOe and Pro ASIC3E Devices

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This current draw can occur in the following cases:

•

In Active and Static modes:

–

Input buffers with pull-up, driven LOW

–

Input buffers with pull-down, driven HIGH

–

Bidirectional buffers with pull-up, driven LOW

–

Bidirectional buffers with pull-down, driven HIGH

–

Output buffers with pull-up, driven LOW

–

Output buffers with pull-down, driven HIGH

–

Tristate buffers with pull-up, driven LOW

–

Tristate buffers with pull-down, driven HIGH

•

In Flash*Freeze mode:

–

Input buffers with pull-up, driven LOW

–

Input buffers with pull-down, driven HIGH

–

Bidirectional buffers with pull-up, driven LOW

–

Bidirectional buffers with pull-down, driven HIGH

Electrostatic Discharge Protection

Low-power flash devices are tested per JEDEC Standard JESD22-A114-B.

These devices contain clamp diodes at every I/O, global, and power pad. Clamp diodes protect all

device pads against damage from ESD as well as from excessive voltage transients.

All IGLOO and ProASIC3 devices are tested to the following models: the Human Body Model (HBM)

with a tolerance of 2,000 V, the Machine Model (MM) with a tolerance of 250 V, and the Charged

Device Model (CDM) with a tolerance of 200 V.

Each I/O has two clamp diodes. One diode has its positive (P) side connected to the pad and its

connected to the pad. During operation, these diodes are normally biased in the off state, except

In 30 k gate devices, the first diode is always off. In other devices, the clamp diode is always on and

cannot be switched off.

By selecting the appropriate I/O configuration, the diode is turned on or off. Refer to Table 13 for

more information about the I/O standards and the clamp diode.

The second diode is always connected to the pad, regardless of the I/O configuration selected.

Table 13 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in IGLOOe and ProASIC3E Devices

I/O Assignment

Clamp Diode

Hot Insertion

5 V Input

Tolerance

Input

Buffer

Output

Buffer

3.3 V LVTTL/LVCMOS

No

Yes

Enabled/Disabled

3.3 V PCI, 3.3 V PCI-X

Yes

No

Enabled/Disabled

No

Yes

No

Enabled/Disabled

Yes

No

Enabled/Disabled

LVCMOS 1.8 V

No

Yes

No

Enabled/Disabled

LVCMOS 1.5 V

No

Yes

No

Enabled/Disabled

Voltage-Referenced Input Buffer

No

Yes

No

Enabled/Disabled

Differential, LVDS/B-LVDS/M-LVDS/LVPECL

No

Yes

No

Enabled/Disabled

Notes:

1. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor.

2. In the SmartGen Core Reference Guide, select the LVCMOS5 macro for the LVCMOS 2.5 V / 5.0 V I/O

standard or the LVCMOS25 macro for the LVCMOS 2.5 V I/O standard.

3. Can be implemented with an external resistor and an internal clamp diode.