PROASIC3E datasheet(12/37 Pages) ACTEL

12 / 37 page

I/O Structures in IGLOOe and ProASIC3E Devices

v1.4

3.3 V PCI-X (Peripheral Component Interface Extended)

An enhanced version of the PCI specification, 3.3 V PCI-X can support higher average bandwidths;

it increases the speed that data can move within a computer from 66 MHz to 133 MHz. It is

backward-compatible, which means devices can operate at conventional PCI frequencies (33 MHz

and 66 MHz). PCI-X is more fault-tolerant than PCI. It also does not have programmable drive

strength.

Voltage-Referenced Standards

I/Os using these standards are referenced to an external reference voltage (VREF) and are supported

on E devices only.

HSTL Class I and II (High-Speed Transceiver Logic)

These are general-purpose, high-speed 1.5 V bus standards (EIA/JESD 8-6) for signaling between

integrated circuits. The signaling range is 0 V to 1.5 V, and signals can be either single-ended or

differential. HSTL requires a differential amplifier input buffer and a push-pull output buffer. The

reference voltage (VREF) is 0.75 V. These standards are used in the memory bus interface with data

switching capability of up to 400 MHz. The other advantages of these standards are low power and

fewer EMI concerns.

HSTL has four classes, of which low-power flash devices support Class I and II. These classes are

defined by standard EIA/JESD 8-6 from the Electronic Industries Alliance (EIA):

•

Class I – Unterminated or symmetrically parallel-terminated

•

Class II – Series-terminated

•

Class III – Asymmetrically parallel-terminated

•

Class IV – Asymmetrically double-parallel-terminated

SSTL2 Class I and II (Stub Series Terminated Logic 2.5 V)

These are general-purpose 2.5 V memory bus standards (JESD 8-9) for driving transmission lines,

designed specifically for driving the DDR SDRAM modules used in computer memory. SSTL2

requires a differential amplifier input buffer and a push-pull output buffer. The reference voltage

(VREF) is 1.25 V.

SSTL3 Class I and II (Stub Series Terminated Logic 3.3 V)

These are general-purpose 3.3 V memory bus standards (JESD 8-8) for driving transmission lines.

SSTL3 requires a differential amplifier input buffer and a push-pull output buffer. The reference

voltage (VREF) is 1.5 V.

Figure 7 • SSTL and HSTL Topology

OUT

GND

VREF

VCCI

Device 1

Device 2

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