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PROASIC3E датащи(PDF) 20 Page - Actel Corporation

номер детали PROASIC3E
подробное описание детали  I/O Structures in IGLOOe and ProASIC3E Devices
PDF  37 Pages
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производитель  ACTEL [Actel Corporation]
домашняя страница  http://www.actel.com
Logo ACTEL - Actel Corporation

PROASIC3E датащи(HTML) 20 Page - Actel Corporation

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I/O Structures in IGLOOe and ProASIC3E Devices
20
v1.4
5 V Input and Output Tolerance
IGLOO and ProASIC3 devices are both 5 V-input– and 5 V–output–tolerant if certain I/O standards
are selected. Table 6 on page 6 shows the I/O standards that support 5 V input tolerance. Only 3.3 V
LVTTL/LVCMOS standards support 5 V output tolerance. Refer to the appropriate family datasheet
for detailed description and configuration information.
This feature is not shown in the I/O Attribute Editor.
5 V Input Tolerance
I/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, LVCMOS 2.5 V, and LVCMOS
2.5 V / 5.0 V configurations are used (see Table 13 on page 19). There are four recommended
solutions for achieving 5 V receiver tolerance (see Figure 10 on page 21 to Figure 13 on page 23 for
details of board and macro setups). All the solutions meet a common requirement of limiting the
voltage at the input to 3.6 V or less. In fact, the I/O absolute maximum voltage rating is 3.6 V, and
any voltage above 3.6 V may cause long-term gate oxide failures.
Solution 1
The board-level design must ensure that the reflected waveform at the pad does not exceed the
limits provided in the recommended operating conditions in the datasheet. This is a requirement to
ensure long-term reliability.
This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used
for clamping, and the voltage must be limited by the two external resistors as explained below.
Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
This solution requires two board resistors, as demonstrated in Figure 10 on page 21. Here are some
examples of possible resistor values (based on a simplified simulation model with no line effects
and
10
Ω transmitter
output
resistance,
where
Rtx_out_high = [VCCI –VOH]/ IOH
and
Rtx_out_low = VOL /IOL).
Example 1 (high speed, high current):
Rtx_out_high = Rtx_out_low = 10
R1 = 36
Ω (±5%), P(r1)min = 0.069 Ω
R2 = 82
Ω (±5%), P(r2)min = 0.158 Ω
Imax_tx = 5.5 V / (82 × 0.95 + 36 × 0.95 + 10) = 45.04 mA
tRISE = tFALL = 0.85 ns at C_pad_load = 10 pF (includes up to 25% safety margin)
tRISE = tFALL = 4 ns at C_pad_load = 50 pF (includes up to 25% safety margin)
Example 2 (low-medium speed, medium current):
Rtx_out_high = Rtx_out_low = 10
R1 = 220
Ω (±5%), P(r1)min = 0.018 Ω
R2 = 390
Ω (±5%), P(r2)min = 0.032 Ω
Imax_tx = 5.5 V / (220 × 0.95 + 390 × 0.95 + 10) = 9.17 mA
tRISE = tFALL = 4 ns at C_pad_load = 10 pF (includes up to 25% safety margin)
tRISE = tFALL = 20 ns at C_pad_load = 50 pF (includes up to 25% safety margin)
Other values of resistors are also allowed as long as the resistors are sized appropriately to limit the
voltage at the receiving end to 2.5 V < Vin(rx) < 3.6 V when the transmitter sends a logic 1. This
range of Vin_dc(rx) must be assured for any combination of transmitter supply (5 V ± 0.5 V),
transmitter output resistance, and board resistor tolerances.
Temporary overshoots are allowed according to the overshoot and undershoot table in the
datasheet.



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