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PROASIC3E датащи(PDF) 8 Page - Actel Corporation

номер детали PROASIC3E
подробное описание детали  I/O Structures in IGLOOe and ProASIC3E Devices
PDF  37 Pages
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производитель  ACTEL [Actel Corporation]
домашняя страница  http://www.actel.com
Logo ACTEL - Actel Corporation

PROASIC3E датащи(HTML) 8 Page - Actel Corporation

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I/O Structures in IGLOOe and ProASIC3E Devices
8v1.4
I/O Architecture
I/O Tile
The I/O tile provides a flexible, programmable structure for implementing a large number of I/O
standards. In addition, the registers available in the I/O tile can be used to support high-
performance register inputs and outputs, with register enable if desired (Figure 3). The registers
can also be used to support the JESD-79C Double Data Rate (DDR) standard within the I/O structure
(see DDR for Actel’s Low-Power Flash Devices for more information).
As depicted in Figure 3, all I/O registers share one CLR port. The output register and output enable
register share one CLK port.
Figure 3 • I/O Block Logical Representation
Input
Register
E = Enable Pin
A
Y
PAD
1
2
3
4
5
6
OCE
ICE
ICE
Input
Register
Input
Register
CLR/PRE
CLR/PRE
CLR/PRE
CLR/PRE
CLR/PRE
Pull-Up/-Down
Resistor Control
Signal Drive Strength
and Slew Rate Control
Output
Register
Output
Register
To FPGA Core
From FPGA Core
Output
Enable
Register
OCE
I/O / CLR or I/O / PRE / OCE
I/O / Q0
I/O / Q1
I/O / ICLK
I/O / D0
I/O / D1 / ICE
I/O / OCLK
I/O / OE



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