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PROASIC3E датащи(PDF) 10 Page - Actel Corporation

номер детали PROASIC3E
подробное описание детали  I/O Structures in IGLOOe and ProASIC3E Devices
PDF  37 Pages
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производитель  ACTEL [Actel Corporation]
домашняя страница  http://www.actel.com
Logo ACTEL - Actel Corporation

PROASIC3E датащи(HTML) 10 Page - Actel Corporation

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I/O Structures in IGLOOe and ProASIC3E Devices
10
v1.4
I/O Registers
Each I/O module contains several input, output, and enable registers. Refer to Figure 5 for a
simplified representation of the I/O block. The number of input registers is selected by a set of
switches (not shown in Figure 3 on page 8) between registers to implement single-ended or
differential data transmission to and from the FPGA core. The Designer software sets these
switches for the user. A common CLR/PRE signal is employed by all I/O registers when I/O register
combining is used. Input Register 2 does not have a CLR/PRE pin, as this register is used for DDR
implementation. The I/O register combining must satisfy certain rules.
Notes:
1. All NMOS transistors connected to the I/O pad serve as ESD protection.
2. See Table 2 on page 3 for available I/O standards.
Figure 5 • Simplified I/O Buffer Circuitry
Programmable Input
Delay Control
Input Buffer Standard2
and Schmitt Trigger
Control
Input Signal to Core Logic
Input Buffer
OE
(from core logic)
Output Signal
(from core logic)
Output Buffer
Logic and
Enable Skew
Circuit
Drive
Strength
and
Output
Slew Rate
Control
Clamp Diode
ESD Protection1
Weak
Pull-
Down
Control
(from
core)
Clamp Diode
ESD Protection1
VCCI
I/O PAD
Weak
Pull-Up
Control
(from
core)
Hot-Swap, 5 V Tolerance, and
Clamp Diode Control
Output Buffer
VCCI
VCCI



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