I/O Structures in IGLOOe and ProASIC3E Devices

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5 V Output Tolerance

IGLOO and ProASIC3 I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS mode to reliably drive 5 V TTL

receivers. It is also critical that there be NO external I/O pull-up resistor to 5 V, since this resistor

would pull the I/O pad voltage beyond the 3.6 V absolute maximum value and consequently cause

damage to the I/O.

When set to 3.3 V LVTTL or 3.3 V LVCMOS mode, the I/Os can directly drive signals into 5 V TTL

will be recognized correctly by 5 V TTL receivers.

Schmitt Trigger

A Schmitt trigger is a buffer used to convert a slow or noisy input signal into a clean one before

passing it to the FPGA. Using Schmitt trigger buffers guarantees a fast, noise-free input signal to

the FPGA.

ProASIC3E devices have Schmitt triggers built into their I/O circuitry. The Schmitt trigger is available

for the LVTTL, LVCMOS, and 3.3 V PCI I/O standards.

This feature can be implemented by using a Physical Design Constraints (PDC) command (Table 6 on

page 6) or by selecting a check box in the I/O Attribute Editor in Designer. The check box is cleared

by default.

Selectable Skew between Output Buffer Enable and Disable Times

Low-power flash devices have a configurable skew block in the output buffer circuitry that can be

enabled to delay output buffer assertion without affecting deassertion time. Since this skew block

is only available for the OE signal, the feature can be used in tristate and bidirectional buffers. A

typical 1.2 ns delay is added to the OE signal to prevent potential bus contention. Refer to the

appropriate family datasheet for detailed timing diagrams and descriptions.

The Skew feature is available for all I/O standards.

This feature can be implemented by using a PDC command (Table 6 on page 6) or by selecting a

check box in the I/O Attribute Editor in Designer. The check box is cleared by default.

The configurable skew block is used to delay output buffer assertion (enable) without affecting

deassertion (disable) time.

Figure 14 • Block Diagram of Output Enable Path

ENABLE (OUT)

Skew Circuit

Output Enable

(from FPGA core)

I/O Output

Buffers

ENABLE (IN)

MUX

Skew Select