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UPSD3233 датащи(PDF) 110 Page - STMicroelectronics

номер детали UPSD3233
подробное описание детали  Flash Programmable System Devices with 8032 Microcontroller Core
PDF  170 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD3233 датащи(HTML) 110 Page - STMicroelectronics

Back Button UPSD3233 Datasheet HTML 106Page - STMicroelectronics UPSD3233 Datasheet HTML 107Page - STMicroelectronics UPSD3233 Datasheet HTML 108Page - STMicroelectronics UPSD3233 Datasheet HTML 109Page - STMicroelectronics UPSD3233 Datasheet HTML 110Page - STMicroelectronics UPSD3233 Datasheet HTML 111Page - STMicroelectronics UPSD3233 Datasheet HTML 112Page - STMicroelectronics UPSD3233 Datasheet HTML 113Page - STMicroelectronics UPSD3233 Datasheet HTML 114Page - STMicroelectronics Next Button
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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
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Separate Space Mode. Program space is sepa-
rated from Data space. For example, Program Se-
lect Enable (PSEN) is used to access the program
code from the primary Flash memory, while READ
Strobe (RD) is used to access data from the sec-
ondary Flash memory, SRAM and I/O Port blocks.
This configuration requires the VM Register to be
set to 0Ch (see Figure 55).
Combined Space Modes. The
Program
and
Data spaces are combined into one memory
space that allows the primary Flash memory, sec-
ondary Flash memory, and SRAM to be accessed
by either Program Select Enable (PSEN) or READ
Strobe (RD). For example, to configure the prima-
ry Flash memory in Combined space, Bits b2 and
b4 of the VM Register are set to '1' (see Figure 56).
Figure 55. Separate Space Mode
Figure 56. Combined Space Mode
Primary
Flash
Memory
DPLD
Secondary
Flash
Memory
SRAM
RS0
CSBOOT0-3
FS0-FS7
CS
CS
CS
OE
OE
RD
PSEN
OE
AI02869C
Primary
Flash
Memory
DPLD
Secondary
Flash
Memory
SRAM
RS0
CSBOOT0-3
FS0-FS7
RD
CS
CS
CS
RD
OE
OE
VM REG BIT 2
PSEN
VM REG BIT 0
VM REG BIT 1
VM REG BIT 3
VM REG BIT 4
OE
AI02870C



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