UPSD3233 datasheet(54/170 Pages) STMICROELECTRONICS

54 / 170 page

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

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Table 41. Description of the T2CON Bits

Note: 1. The RCLK1 and TCLK1 Bits in the PCON Register control UART 2, and have the same function as RCLK and TCLK.

Table 42. Timer/Counter2 Operating Modes

Note:

↓ = falling edge

Bit

Symbol

Function

7TF2

Timer 2 overflow flag. Set by a Timer 2 overflow, and must be cleared by software. TF2

will not be set when either (RCLK, RCLK1)=1 or (TCLK, TCLK)=1

6EXF2

Timer 2 external flag set when either a capture or reload is caused by a negative

transition on T2EX and EXEN2=1. When Timer 2 Interrupt is enabled, EXF2=1 will

cause the CPU to vector to the Timer 2 Interrupt routine. EXF2 must be cleared by

software

RCLK(1)

Receive clock flag (UART 1). When set, causes the serial port to use Timer 2 overflow

pulses for its receive clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be

used for the receive clock

TCLK(1)

Transmit clock flag (UART 1). When set, causes the serial port to use Timer 2 overflow

pulses for its transmit clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be

used for the transmit clock

EXEN2

Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of

a negative transition on T2EX if Timer 2 is not being used to clock the serial port.

EXEN2=0 causes Time 2 to ignore events at T2EX

TR2

Start/stop control for Timer 2. A logic 1 starts the timer

1C/T2

Timer or Counter select for Timer 2. Cleared for timer operation (input from internal

system clock, tCPU); set for external event counter operation (negative edge triggered)

0CP/RL2

Capture/reload flag. When set, capture will occur on negative transition of T2EX if

EXEN2=1. When cleared, auto-reload will occur either with TImer 2 overflows, or

negative transitions of T2EX when EXEN2=1. When either (RCLK, RCLK1)=1 or (TCLK,

TCLK)=1, this bit is ignored, and timer is forced to auto-reload on Timer 2 overflow

Mode

T2CON

T2MOD

DECN

T2CON

EXEN

P1.1

T2EX

Remarks

Input Clock

RxCLK

TxCLK

CP/

RL2

TR2

Internal

External

(P1.0/T2)

16-bit

Auto-

reload

reload upon overflow

fOSC/12

MAX

fOSC/24

↓

reload trigger (falling edge)

Down counting

Up counting

16-bit

Capture

16-bit Timer/Counter

(only up counting)

fOSC/12

MAX

fOSC/24

↓

Capture (TH1,TL2)

→

(RCAP2H,RCAP2L)

Baud Rate

Generator

No overflow interrupt

request (TF2)

fOSC/12

MAX

fOSC/24

↓

Extra External Interrupt

(Timer 2)

Off

Timer 2 stops

—

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