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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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UPSD3233 датащи(PDF) 46 Page - STMicroelectronics |
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UPSD3233 датащи(HTML) 46 Page - STMicroelectronics |
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46 / 170 page  uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV 46/170 External Reset The RESET pin is connected to a Schmitt trigger for noise reduction. A RESET is accomplished by holding the RESET pin LOW for at least 1ms at power up while the oscillator is running. Refer to AC spec on other RESET timing requirements. Low VDD Voltage Reset An internal reset is generated by the LVR circuit when the VDD drops below the reset threshold. Af- ter VDD reaching back up to the reset threshold, the RESET signal will remain asserted for 10ms before it is released. On initial power-up the LVR is enabled (default). After power-up the LVR can be disabled via the LVREN Bit in the PCON Reg- ister. Note: The LVR logic is still functional in both the Idle and Power-down Modes. The reset threshold: ■ 5V operation: 4V +/- 0.25V ■ 3.3V operation: 2.5V +/-0.2V This logic supports approximately 0.1V of hystere- sis and 1µs noise-cancelling delay. Watchdog Timer Overflow The Watchdog timer generates an internal reset when its 22-bit counter overflows. See Watchdog Timer section for details. USB Reset The USB reset is generated by a detection on the USB bus RESET signal. A single-end zero on its upstream port for 4 to 8 times will set RSTF Bit in UISTA register. If Bit 6 (RSTE) of the UIEN Regis- ter is set, the detection will also generate the RESET signal to reset the CPU and other periph- erals in the MCU. |
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