UPSD3233 datasheet(59/170 Pages) STMICROELECTRONICS

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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

As data bits shift out to the right, zeros come in

from the left. When the MSB of the data byte is at

the output position of the shift register, then the '1'

that was initially loaded into the 9th position, is just

to the left of the MSB, and all positions to the left

of that contain zeros. This condition flags the TX

Control block to do one last shift and then deacti-

vate SEND and set T1. Both of these actions occur

at S1P1. Both of these actions occur at S1P1 of

the 10th machine cycle after “WRITE to SBUF.”

Reception is initiated by the condition REN = 1 and

R1 = 0. At S6P2 of the next machine cycle, the RX

Control unit writes the bits 11111110 to the receive

shift register, and in the next clock phase activates

RECEIVE.

RECEIVE enables SHIFT CLOCK to the alternate

output function line of TxD. SHIFT CLOCK makes

transitions at S3P1 and S6P1 of every machine

cycle in which RECEIVE is active, the contents of

the receive shift register are shifted to the left one

position. The value that comes in from the right is

the value that was sampled at the RxD pin at S5P2

of the same machine cycle.

As data bits come in from the right, '1s' shift out to

the left. When the '0' that was initially loaded into

the right-most position arrives at the left-most po-

sition in the shift register, it flags the RX Control

block to do one last shift and load SBUF. At S1P1

of the 10th machine cycle after the WRITE to

SCON that cleared RI, RECEIVE is cleared as RI

is set.

More About Mode 1. Ten bits are transmitted

(through TxD), or received (through RxD): a start

Bit (0), 8 data bits (LSB first). and a Stop Bit (1). On

receive, the Stop Bit goes into RB8 in SCON. In

the uPSD323X Devices the baud rate is deter-

mined by the Timer 1 or Timer 2 over-flow rate.

Figure 29., page 62 shows a simplified functional

diagram of the serial port in Mode 1, and associat-

ed timings for transmit receive.

Transmission is initiated by any instruction that

uses SBUF as a destination register. The “WRITE

to SBUF” signal also loads a '1' into the 9th bit po-

sition of the transmit shift register and flags the TX

Control unit that a transmission is requested.

Transmission actually commences at S1P1 of the

machine cycle following the next rollover in the di-

vide-by-16 counter. (Thus, the bit times are syn-

chronized to the divide-by-16 counter, not to the

“WRITE to SBUF” signal.)

The transmission begins with activation of SEND

which puts the start bit at TxD. One bit time later,

DATA is activated, which enables the output bit of

the transmit shift register to TxD. The first shift

pulse occurs one bit time after that.

As data bits shift out to the right, zeros are clocked

in from the left. When the MSB of the data byte is

at the output position of the shift register, then the

'1' that was initially loaded into the 9th position is

just to the left of the MSB, and all positions to the

left of that contain zeros. This condition flags the

TX Control unit to do one last shift and then deac-

tivate SEND and set TI. This occurs at the 10th di-

vide-by-16 rollover after “WRITE to SBUF.”

Reception is initiated by a detected 1-to-0 transi-

tion at RxD. For this purpose RxD is sampled at a

rate of 16 times whatever baud rate has been es-

tablished. When a transition is detected, the di-

vide-by-16 counter is immediately reset, and 1FFH

is written into the input shift register. Resetting the

divide-by-16 counter aligns its roll-overs with the

boundaries of the incoming bit times.

The 16 states of the counter divide each bit time

into 16ths. At the 7th, 8th, and 9th counter states

of each bit time, the bit detector samples the value

of RxD. The value accepted is the value that was

seen in at least 2 of the 3 samples. This is done for

noise rejection. If the value accepted during the

first bit time is not '0,' the receive circuits are reset

and the unit goes back to looking for an-other 1-to-

0 transition. This is to provide rejection of false

start bits. If the start bit proves valid, it is shifted

into the input shift register, and reception of the re-

set of the rest of the frame will proceed.

As data bits come in from the right, '1s' shift out to

the left. When the start bit arrives at the left-most

position in the shift register (which in Mode 1 is a

9-bit register), it flags the RX Control block to do

one last shift, load SBUF and RB8, and set RI. The

signal to load SBUF and RB8, and to set RI, will be

generated if, and only if, the following conditions

are met at the time the final shift pulse is generat-

ed:

R1 = 0, and

Either SM2 = 0, or the received Stop Bit = 1.

If either of these two conditions is not met, the re-

ceived frame is irretrievably lost. If both conditions

are met, the Stop Bit goes into RB8, the 8 data bits

go into SBUF, and RI is activated. At this time,

whether the above conditions are met or not, the

unit goes back to looking for a 1-to-0 transition in

RxD.

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