UPSD3233 datasheet(106/170 Pages) STMICROELECTRONICS

106 / 170 page

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

106/170

Unlock Bypass. The Unlock Bypass instructions

allow the system to program bytes to the Flash

memories faster than using the standard Program

instruction. The Unlock Bypass Mode is entered

by first initiating two Unlock cycles. This is followed

by a third WRITE cycle containing the Unlock By-

pass code, 20h (as shown in Table 85., page 101).

The Flash memory then enters the Unlock Bypass

Mode. A two-cycle Unlock Bypass Program in-

struction is all that is required to program in this

mode. The first cycle in this instruction contains

the Unlock Bypass Program code, A0h. The sec-

ond cycle contains the program address and data.

Additional data is programmed in the same man-

ner. These instructions dispense with the initial

two Unlock cycles required in the standard Pro-

gram instruction, resulting in faster total Flash

memory programming.

During the Unlock Bypass Mode, only the Unlock

Bypass Program and Unlock Bypass Reset Flash

instructions are valid.

To exit the Unlock Bypass Mode, the system must

issue the two-cycle Unlock Bypass Reset Flash in-

struction. The first cycle must contain the data

90h; the second cycle the data 00h. Addresses are

Don’t Care for both cycles. The Flash memory

then returns to READ Mode.

Erasing Flash Memory

Flash Bulk Erase. The Flash Bulk Erase instruc-

tion uses six WRITE operations followed by a

READ operation of the status register, as de-

scribed in Table 85. If any byte of the Bulk Erase

instruction is wrong, the Bulk Erase instruction

aborts and the device is reset to the READ Flash

memory status.

During a Bulk Erase, the memory status may be

checked by reading the Error Flag Bit (DQ5), the

Toggle Flag Bit (DQ6), and the Data Polling Flag

Bit (DQ7), as detailed in Programming Flash

Memory, page 104. The Error Flag Bit (DQ5) re-

turns a '1' if there has been an Erase Failure (max-

imum

number

Erase

cycles

have

been

executed).

It is not necessary to program the memory with

00h because the PSD Module automatically does

this before erasing to 0FFh.

During execution of the Bulk Erase instruction, the

Flash memory does not accept any instructions.

Flash Sector Erase. The Sector Erase instruc-

tion uses six WRITE operations, as described in

Table 85., page 101. Additional Flash Sector

Erase codes and Flash memory sector addresses

can be written subsequently to erase other Flash

memory sectors in parallel, without further coded

cycles, if the additional bytes are transmitted in a

shorter time than the time-out period of about

100µs. The input of a new Sector Erase code re-

starts the time-out period.

The status of the internal timer can be monitored

through the level of the Erase Time-out Flag Bit

(DQ3). If the Erase Time-out Flag Bit (DQ3) is '0,'

the Sector Erase instruction has been received

and the time-out period is counting. If the Erase

Time-out Flag Bit (DQ3) is '1,' the time-out period

has expired and the embedded algorithm is busy

erasing the Flash memory sector(s). Before and

during Erase time-out, any instruction other than

Suspend Sector Erase and Resume Sector Erase

instructions abort the cycle that is currently in

progress, and reset the device to READ Mode.

During a Sector Erase, the memory status may be

checked by reading the Error Flag Bit (DQ5), the

Toggle Flag Bit (DQ6), and the Data Polling Flag

Bit (DQ7), as detailed in Programming Flash

Memory, page 104.

During execution of the Erase cycle, the Flash

memory accepts only RESET and Suspend Sec-

tor Erase instructions. Erasure of one Flash mem-

ory sector may be suspended, in order to read

data from another Flash memory sector, and then

resumed.

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