UPSD3233 datasheet(58/170 Pages) STMICROELECTRONICS

58 / 170 page

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

58/170

Table 45. Timer 1-Generated Commonly Used Baud Rates

The timer can be configured for either “timer” or

“counter” operation. In the most typical applica-

tions, it is configured for “timer” operation (C/T2 =

0). “Timer” operation is a little different for Timer 2

when it’s being used as a baud rate generator.

Normally, as a timer it would increment every ma-

chine cycle (thus at the 1/6 the CPU clock frequen-

cy). In the case, the baud rate is given by the

formula:

Mode 1,3 Baud Rate =

fOSC / (32 x [65536 – (RCAP2H, RCAP2L)]

where (RCAP2H, RCAP2L) is the content of

RC2H and RC2L taken as a 16-bit unsigned inte-

ger.

Timer 2 also be used as the Baud Rate Generating

Mode. This mode is valid only if RCLK + TCLK = 1

in T2CON or in PCON.

Note: A roll-over in TH2 does not set TF2, and will

not generate an interrupt. Therefore, the Timer In-

terrupt does not have to be disabled when Timer 2

is in the Baud Rate Generator Mode.

Note: If EXEN2 is set, a 1-to-0 transition in T2EX

will set EXF2 but will not cause a reload from

(RCAP2H, RCAP2L) to (TH2, TL2). Thus when

Timer 2 is in use as a baud rate generator, T2EX

can be used as an extra external interrupt, if de-

sired.

It should be noted that when Timer 2 is running

(TR2 = 1) in “timer” function in the Baud Rate Gen-

erator Mode, one should not try to READ or

WRITE TH2 or TL2. Under these conditions the

timer is being incremented every state time, and

the results of a READ or WRITE may not be accu-

rate. The RC registers may be read, but should not

be written to, because a WRITE might overlap a

reload and cause WRITE and/or reload errors.

Turn the timer off (clear TR2) before accessing the

Timer 2 or RC registers, in this case.

More About Mode 0. Serial data enters and exits

through RxD. TxD outputs the shift clock. 8 bits are

transmitted/received: 8 data bits (LSB first). The

baud rate is fixed at 1/12 the fOSC.

Figure 27., page 61 shows a simplified functional

diagram of the serial port in Mode 0, and associat-

ed timing.

Transmission is initiated by any instruction that

uses SBUF as a destination register. The “WRITE

to SBUF” signal at S6P2 also loads a '1' into the

9th position of the transmit shift register and tells

the TX Control block to commence a transmission.

The internal timing is such that one full machine

cycle will elapse between “WRITE to SBUF” and

activation of SEND.

SEND enables the output of the shift register to the

alternate out-put function line of RxD and also en-

able SHIFT CLOCK to the alternate output func-

tion line of TxD. SHIFT CLOCK is low during S3,

S4, and S5 of every machine cycle, and high dur-

ing S6, S1, and S2. At S6P2 of every machine cy-

cle in which SEND is active, the contents of the

transmit shift are shifted to the right one position.

Baud Rate

fOSC

SMOD

Timer 1

C/T

Mode

Reload Value

Mode 0 Max: 1MHz

12MHz

Mode 2 Max: 375K

12MHz

Modes 1, 3: 62.5K

12MHz

FFh

19.2K

11.059MHz

FDh

9.6K

11.059MHz

FDh

4.8K

11.059MHz

FAh

2.4K

11.059MHz

F4h

1.2K

11.059MHz

E8h

137.5

11.059MHz

1Dh

110

6MHz

72h

110

12MHz

FEEBh

UPSD3233 датащи(PDF) 58 Page - STMicroelectronics

UPSD3233 датащи(HTML) 58 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL