UPSD3233 datasheet(86/170 Pages) STMICROELECTRONICS

86 / 170 page

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

86/170

Table 72. Description of the UCON1 Bits

Table 73. USB Control Register (UCON2: 0ECh)

Table 74. Description of the UCON2 Bits

Table 75. USB Endpoint0 Status Register (USTA: 0EDh)

Bit

Symbol

R/W

Function

7TSEQ1

R/W

Endpoint 1/ Endpoint 2 Transmit Data Packet PID. (0=DATA0, 1=DATA1)

This bit determines which type of data packet (DATA0 or DATA1) will be

sent during the next IN transaction directed to Endpoint 1 or Endpoint 2.

Toggling of this bit must be controlled by software. RESET clears this bit.

EP12SEL

R/W

Endpoint 1/ Endpoint 2 Transmit Selection. (0=Endpoint 1, 1=Endpoint 2)

This bit specifies whether the data inside the registers UDT1 are used for

Endpoint 1 or Endpoint 2. If all the conditions for a successful Endpoint 2

USB response to a hosts IN token are satisfied (TXD1F=0, TX1E=1,

STALL2=0, and EP2E=1) except that the EP12SEL Bit is configured for

Endpoint 1, the USB responds with a NAK handshake packet. RESET

clears this bit.

5TX1E

R/W

Endpoint1 / Endpoint2 Transmit Enable.

This bit enables a transmit to occur when the USB Host Controller send

an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint

enable bit, EP1E or EP2E Bit in the UCON2 register, should also be set.

Software should set the TX1E Bit when data is ready to be transmitted. It

must be cleared by software when no more data needs to be transmitted.

If this bit is '0' or TXD1F is set, the USB will respond with a NAK

handshake to any Endpoint 1 or Endpoint 2 directed IN token.

RESET clears this bit.

4FRESUM

R/W

Force Resume.

This bit forces a resume state (“K” on non-idle state) on the USB data

lines to initiate a remote wake-up. Software should control the timing of

the forced resume to be between 10ms and 15ms. Setting this bit will not

cause the RESUMF Bit to set.

3 to 0

TP1SIZ3 to

TP1SIZ0

R/W

The number of transmit data bytes. These bits are cleared by RESET.

543210

—

SOUT

EP2E

EP1E

STALL2

STALL1

Bit

Symbol

R/W

Function

7 to 5

—

Reserved

4SOUT

R/W

Status out is used to automatically respond to the OUT of a control

READ transfer

EP2E

R/W

Endpoint2 enable. RESET clears this bit

EP1E

R/W

Endpoint1 enable. RESET clears this bit

STALL2

R/W

Endpoint2 Force Stall Bit. RESET clears this bit

STALL1

R/W

Endpoint1 Force Stall Bit. RESET clears this bit

543210

RSEQ

SETUP

OUT

RP0SIZ3

RP0SIZ2

RP0SIZ1

RP0SIZ0

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