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UPSD3233 датащи(PDF) 76 Page - STMicroelectronics |
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UPSD3233 датащи(HTML) 76 Page - STMicroelectronics |
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76 / 170 page ![]() uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV 76/170 Special Function Register for the DDC Interface There are eight SFR in the DDC interface: RAMBUF, DDCCON, DDCADR, DDCDAT are DDC registers. S1CON, S1STA, S1DAT, S1ADR are I2C Inter- face registers, same as the ones described in the standalone I2C bus. DDCDAT Register. DDC1 DATA register for transmission (DDCDAT: 0D5H) ■ 8-bit READ and WRITE register. ■ Indicates DATA BYTE to be transmitted in DDC1 protocol. DDCADR Register. Address pointer for DDC in- terface (DDCADR: 0D6H) ■ 8-bit READ and WRITE register. ■ Address pointer with the capability of the post increment. After each access to RAMBUF register (either by software or by hardware DDC1 interface), the content of this register will be increased by one. It’s available both in DDC1, DDC2 (DDC2B, DDC2B+, and DDC2AB) and system operation. Table 60. DDC SFR Memory Map SFR Addr Reg Name Bit Register Name Reset Value Comments 76 5 4 3 2 1 0 D4 RAMBUF XX DDC Ram Buffer D5 DDCDAT 00 DDC Data xmit register D6 DDCADR 00 Addr pointer register D7 DDCCON — EX_DAT SWENB DDC_AX DDCINT DDC1EN SWHINT M0 00 DDC Control Register |
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