7721 datasheet(116/577 Pages) RENESAS

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7721 Group User’s Manual

INTERRUPTS

7–19

___

7.10 External interrupts (INTi interrupt)

Note: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected.

0 : Interrupt request bit is set to “1”

at “H” level when level sense is

selected; this bit is set to “1” at

falling edge when edge sense is

selected.

1 : Interrupt request bit is set to “1”

at “L” at level when level sense is

selected; this bit is set to “1” at

rising edge when edge sense is

selected.

0 0 0 : Level 0 (Interrupt disabled)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

INT0

to INT2 interrupt control registers (Addresses 7D16 to 7F16)

Bit

Interrupt request bit (Note)

Bit name

At reset

Functions

b2 b1 b0

0 : No interrupt requested

1 : Interrupt requested

Interrupt priority level select bits

Polarity select bit

0 : Edge sense

1 : Level sense

7, 6

–

Undefined

Level sense/Edge sense

select bit

Nothing is assigned.

___

Fig. 7.10.1 Structure of INTi (i=0 to 2) interrupt control register

Bit

Corresponding pin

Functions

INT0

MA8

Port P10 direction register (Address 1816)

At reset

0 : Input mode

1 : Output mode

When using a pin as an input pin

for an external interrupt,clear the

corresponding bit to “0.”

: Bits 3 to 7 are not used for external interrupts.

INT1

INT2

CAS

RAS

MA9

Fig. 7.10.2 Relationship between port P10 direction register and input pins of external interrupt

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