7721 datasheet(115/577 Pages) RENESAS

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7721 Group User’s Manual

INTERRUPTS

7–18

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7.10 External interrupts (INTi interrupt)

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An external interrupt request occurs by an input signal to the INTi (i = 0 to 2) pin. The occurrence factor

of the interrupt request can be selected by the level sense/edge sense select bit and the polarity select bit

(bits 5 and 4 at addresses 7D16 to 7F16) shown in Figure 7.10.1. Table 7.10.1 lists the occurrence factor of

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INTi interrupt request.

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When using P100/INT0 to P102/INT2 pins as input pins of external interrupts, set the corresponding bits at

address 1816 (port P10 direction register) to “0.” (Refer to “Figure 7.10.2.”)

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The signals input to the INTi pin require “H”- or “L”- level width of 250 ns or more, independent of f(XIN).

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Additionally, even when using the pins P100/INT0 to P102/INT2 as the input pins of external interrupts, the

user can obtain the pin’s state by reading bits 0 to 2 at address 1616 (port P10 register).

Note: When selecting an input signal’s falling or “L” level as the occurrence factor of an interrupt request,

make sure that the input signal is held “L” for 250 ns or more. When selecting an input signal’s rising

or “H” level as that, make sure that the input signal is held “H” for 250 ns or more.

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7.10 External interrupts (INTi interrupt)

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Table 7.10.1 Occurrence factor of INTi interrupt request

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INTi interrupt request occurrence factor

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The INTi interrupt request occurs by detecting the state of pin INTi all the time. Therefore, when the user

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does not use the INTi interrupt, set the INTi interrupt’s priority level to level 0.

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Interrupt request occurs at the falling edge of a signal input to pin INTi (Edge sense).

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Interrupt request occurs at the rising edge of a signal input to pin INTi (Edge sense).

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Interrupt request occurs when pin INTi is at “H” level (Level sense).

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Interrupt request occurs when pin INTi is at “L” level (Level sense).

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