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7721 Group User’s Manual

INTERRUPTS

7–22

Fig. 7.11.1 Program example to reserve time required for change of interrupt priority level

Table 7.11.1 Correspondence between number of instructions to be inserted in Figure 7.11.1 and

interrupt priority detection time select bits

7.11 Precautions for interrupts

When changing the interrupt priority level select bits (bits 0 to 2 at addresses 6C16 to 7F16), 2 to 7 cycles

φ are required until the interrupt priority level is changed. Therefore, when the interrupt priority level of

a certain interrupt source is repeatedly changed in a very short time, which consists of a few instructions,

it is necessary to reserve the time required for the change by software. Figure 7.11.1 shows a program

example to reserve the time required for the change. Note that the time required for the change depends

on the contents of the interrupt priority detection time select bits (bits 4 and 5 at address 5E16). Table 7.11.1

lists the correspondence between the number of instructions inserted in Figure 7.11.1 and the interrupt

priority detection time select bits.

Interrupt priority detection time select bits (Note)

Interrupt priority level

detection time

7 cycles of

4 cycles of

2 cycles of

Do not select.

Number of inserted

NOP instructions

4 or more

2 or more

1 or more

Note: We recommend [b5 = “1”, b4 = “0”].

; Write instruction for the interrupt priority level select bits

; Inserted NOP instruction (Note)

;

; Write instruction for the interrupt priority level select bits

Note: Except the write instruction for address XX , any instruction which has the same

cycles as the NOP instruction can also be inserted.

For the number of inserted NOP instructions, refer to “Table 7.11.1.”

XX: any of 6C to 7F

LDM.B #0XH, 00XXH

NOP

LDM.B #0XH, 00XXH

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