7721 datasheet(9/577 Pages) RENESAS

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7721 Group User’s Manual

Table of contents

CHAPTER 4 RESET

4.1 Hardware reset ...................................................................................................................... 4-2

4.1.1 Pin state .......................................................................................................................... 4-3

4.1.2 State of CPU, SFR area, and internal RAM area..................................................... 4-4

4.1.3 Internal processing sequence after reset ................................................................. 4-11

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4.1.4 Time supplying “L” level to RESET pin .................................................................... 4-12

4.2 Software reset ...................................................................................................................... 4-13

CHAPTER 5 CLOCK GENERATING CIRCUIT

5.1 Oscillation circuit examples ............................................................................................... 5-2

5.1.1 Connection example using resonator/oscillator .......................................................... 5-2

5.1.2 Externally generated clock input example .................................................................. 5-2

5.2 Clocks .......................................................................................................................................5-3

5.2.1 Clocks generated in clock generating circuit ............................................................. 5-4

5.3 Stop mode .............................................................................................................................. 5-5

5.3.1 Stop mode ...................................................................................................................... 5-5

[Precautions for Stop mode] .................................................................................................. 5-8

5.4 Wait mode ............................................................................................................................... 5-9

5.4.1 Wait mode ...................................................................................................................... 5-9

[Precautions for Wait mode] ................................................................................................. 5-11

CHAPTER 6 INPUT/OUTPUT PINS

6.1 Overview ..................................................................................................................................6-2

6.2 Programmable I/O ports ...................................................................................................... 6-2

6.2.1 Direction register ............................................................................................................ 6-3

6.2.2 Port register .................................................................................................................... 6-4

6.3 Examples of handling unused pins .................................................................................. 6-7

CHAPTER 7 INTERRUPTS

7.1 Overview ..................................................................................................................................7-2

7.2 Interrupt sources ................................................................................................................... 7-4

7.3 Interrupt control .................................................................................................................... 7-5

7.3.1 Interrupt disable flag (I) ................................................................................................ 7-7

7.3.2 Interrupt request bit ....................................................................................................... 7-7

7.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL) ....... 7-7

7.4 Interrupt priority level .......................................................................................................... 7-9

7.5 Interrupt priority level detection circuit ........................................................................ 7-10

7.6 Interrupt priority level detection time ............................................................................ 7-12

7.7 Sequence from acceptance of interrupt request until execution of interrupt

routine .................................................................................................................................... 7-13

7.7.1 Change in IPL at acceptance of interrupt request .................................................. 7-14

7.7.2 Push operation for registers ....................................................................................... 7-15

7.8 Return from interrupt routine ........................................................................................... 7-16

7.9 Multiple interrupts ............................................................................................................... 7-16

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7.10 External interrupts (INTi interrupt) ............................................................................... 7-18

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7.10.1 Functions of INTi interrupt request bit .................................................................... 7-20

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7.10.2 Switching of INTi interrupt request occurrence factor .......................................... 7-21

7.11 Precautions for interrupts ............................................................................................... 7-22

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