7721 datasheet(44/577 Pages) RENESAS

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CENTRAL PROCESSING UNIT (CPU)

7721 Group User’s Manual

2–21

2.4 Memory assignment

Fig. 2.4.3 SFR area’s memory map (2)

001FC016

001FC116

001FC216

001FC316

001FC416

001FC516

001FC616

001FC716

001FC816

001FC916

001FD016

001FD116

001FD216

001FD316

001FD416

001FD516

001FD616

001FD716

001FD816

001FD916

001FDA16

001FDB16

001FDC16

001FDD16

001FDE16

001FDF16

001FE016

001FE116

001FE216

001FE316

001FE416

001FE516

001FE616

001FE716

001FE816

001FE916

001FEA16

001FEB16

001FEC16

001FED16

001FEE16

001FEF16

001FF016

001FF116

001FF216

001FF316

001FF416

001FF516

001FF616

001FF716

001FF816

001FF916

001FFA16

001FFB16

001FFC16

001FFD16

001FFE16

001FFF16

001FCB16

001FCC16

001FCD16

001FCE16

001FCF16

001FCA16

Address

Source address register 0

Destination address register 0

Transfer counter register 0

DMA0 mode register L

DMA0 mode register H

DMA0 control register

Source address register 1

Destination address register 1

Transfer counter register 1

DMA1 mode register L

DMA1 mode register H

DMA1 control register

Source address register 2

Destination address register 2

Transfer counter register 2

DMA2 mode register L

DMA2 mode register H

DMA2 control register

Source address register 3

Destination address register 3

Transfer counter register 3

DMA3 mode register L

DMA3 mode register H

DMA3 control register

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