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7721 датащи(PDF) 113 Page - Renesas Technology Corp

номер детали 7721
подробное описание детали  16-BIT SINGLE-CHIP MICROCOMPUTER
PDF  577 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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7721 Group User’s Manual
INTERRUPTS
7–16
7.8 Return from interrupt routine
When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank
register (PG), program counter (PC), and processor status register (PS) which were pushed onto the stack
area just before the INTACK sequence, are automatically pulled. After this, the control returns to the original
routine. And then, the suspended processing, which was in progress before the acceptance of the interrupt
request, is resumed.
Before the RTI instruction is executed, pull registers which were pushed by software in the interrupt routine,
using the PUL instruction, etc.
7.9 Multiple interrupts
Just after a branch is made to an interrupt routine, the following occur:
•Interrupt disable flag (I) = “1” (Interrupts are disabled)
•Interrupt request bit of accepted interrupt = “0”
•Processor interrupt priority level (IPL) = Interrupt priority level of accepted interrupt
Accordingly, as long as the IPL remains unchanged, an interrupt request whose priority level is higher than
that of the interrupt which is in progress can be accepted by clearing the interrupt disable flag (I) to “0” in
an interrupt routine. In this way, multiple interrupts are processed.
Figure 7.9.1 shows the processing for multiple interrupts.
An interrupt request which has not been accepted because its priority level is lower is held. When the RTI
instruction is executed, the interrupt priority level of the routine which was in progress at acceptance of an
interrupt request is pulled into the IPL. Therefore, if the following relationship is satisfied when interrupt
priority level detection is performed next, the held interrupt request is accepted.
Held interrupt request’s priority level > Processor interrupt priority level (IPL)
7.8 Return from interrupt routine, 7.9 Multiple interrupts



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