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7721 датащи(PDF) 76 Page - Renesas Technology Corp |
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7721 датащи(HTML) 76 Page - Renesas Technology Corp |
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76 / 577 page ![]() 7721 Group User’s Manual RESET 4–13 4.2 Software reset 4.2 Software reset When the power source voltage satisfies the microcomputer’s recommended operating conditions, the microcomputer is reset by writing “1” to the software reset bit (bit 3 at address 5E16). (This is called “ Software reset.”) In this case, the microcomputer initializes pins, CPU, and SFR area just as in the case of a hardware reset. However, the microcomputer retains the contents of the internal RAM area. (Refer to “Table 4.1.1” and “Figures 4.1.3 to 4.1.9.”) Figure 4.2.1 shows the structure of the processor mode register 0 (address 5E16). After completing initialization, the microcomputer performs “internal processing sequence after reset.” (Refer to “Figure 4.1.10.”) After that, it executes a program beginning from the address set into the reset vector addresses (FFFE16 and FFFF16). i Bit Bit name Functions At reset RW 0 1 2 3 4 5 6 7 Software reset bit Interrupt priority detection time select bits Fix this bit to “ 0” Stack bank select bit 0 0 0 0 0 0 The microcomputer is reset by writing “1” to this bit. The value of this bit is “0” at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Do not select. 0 : Bank 016 1 : Bank FF16 0 b5 b4 Processor mode register 0 (Address 5E16) : Bits 0 to 2 and bits 4 to 7 are not used for software reset. b1 b0 b2 b3 b4 b5 b6 b7 0 0 RW RW WO RW RW RW RW Fix this bit to “0” Nothing is assigned. This bit is “1” at reading. 1 Wait bit 0 : Software Wait is inserted when accessing external area. 1 : No software Wait is inserted when accessing external area. Fig. 4.2.1 Structure of processor mode register 0 |
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