7721 datasheet(110/577 Pages) RENESAS

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7721 Group User’s Manual

INTERRUPTS

7–13

7.7 Sequence from acceptance of interrupt request until execution of interrupt routine

The sequence from the acceptance of interrupt request until the execution of the interrupt routine is described

below.

When an interrupt request is accepted, the interrupt request bit of the accepted interrupt is cleared to “0.”

And then, the interrupt processing starts from the cycle just after the completion of the instruction which was

executed at accepting the interrupt request. Figure 7.7.1 shows the sequence from acceptance of interrupt

request to execution of interrupt routine. After execution of an instruction at accepting the interrupt request

is completed, an INTACK (Interrupt Acknowledge) sequence is executed, and a branch is made to the start

address of the interrupt routine allocated in addresses 016 to FFFF16.

The INTACK sequence is automatically performed in the following order.

The contents of the program bank register (PG) just before performing the INTACK sequence are pushed

onto stack.

The contents of the program counter (PC) just before performing the INTACK sequence are pushed onto

stack.

The contents of the processor status register (PS) just before performing the INTACK sequence is

pushed onto stack.

The interrupt disable flag (I) is set to “1.”

The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (IPL).

The contents of the program bank register (PG) are cleared to “0016,” and the contents of the interrupt

vector address are set into the program counter (PC).

Performing the INTACK sequence requires at least 13 cycles of internal clock

φ. Figure 7.7.2 shows the

INTACK sequence timing. After the INTACK sequence is completed, the instruction execution starts from the

start address of the interrupt routine.

7.7 Sequence from acceptance of interrupt request until execution of interrupt routine

@ : Interrupt priority level detection time

Interrupt request occurs.

Interrupt request is accepted.

Instruction

INTACK sequence

Instructions in interrupt routine

Interrupt response time

Time

Time from the occurrence of an interrupt request until the instruction execution which is in progress

at that time is completed.

Time from when execution of an instruction next to begins (Note) until the instruction execution

which is in progress at completion of interrupt priority level detection.

Note: At this time, detection of interrupt priority level begins.

Time required to execute the INTACK sequence (13 cycles of

at minimum)

Fig. 7.7.1 Sequence from acceptance of interrupt request until execution of interrupt routine

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