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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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7721 датащи(PDF) 103 Page - Renesas Technology Corp |
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7721 датащи(HTML) 103 Page - Renesas Technology Corp |
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103 / 577 page  7721 Group User’s Manual INTERRUPTS 7–6 Fig. 7.3.2 Structures of interrupt control register Note: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected. 0 : Interrupt request bit is set to “1” at “H” level when level sense is selected; this bit is set to “1” at falling edge when edge sense is selected. 1 : Interrupt request bit is set to “1” at “L” level when level sense is selected; this bit is set to “1” at rising edge when edge sense is selected. 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b7 b6 b5 b4 b3 b2 b1 b0 INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16) Bit 4 Interrupt request bit (Note) 2 1 0 Bit name At reset 0 RW Functions b2 b1 b0 0 : No interrupt requested 1 : Interrupt requested Interrupt priority level select bits 3 RW RW RW RW RW 0 0 0 0 Polarity select bit 0 : Edge sense 1 : Level sense 7, 6 5 RW – 0 Undefined Level sense/Edge sense select bit Nothing is assigned. 7.3 Interrupt control b7 b6 b5 b4 b3 b2 b1 b0 DMA0 to DMA3, A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2 interrupt control registers (Addresses 6C16 to 7C16) Bit 7 to 4 Interrupt request bit 2 1 0 Bit name At reset 0 RW Functions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 : No interrupt requested 1 : Interrupt requested Interrupt priority level select bits 3 RW RW RW RW – Undefined 0 0 0 Nothing is assigned. |
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