7721 datasheet(101/577 Pages) RENESAS

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7721 Group User’s Manual

INTERRUPTS

7–4

Remarks

Non-maskable

Non-maskable software interrupt

Do not use.

Non-maskable interrupt

Maskable external interrupts

Maskable internal interrupts

Maskable internal interrupt

Maskable internal interrupts

7.2 Interrupt sources

Table 7.2.1 lists the interrupt sources and the interrupt vector addresses. When programming, set the start

address of each interrupt routine at the vector addresses listed in this table.

7.2 Interrupt sources

Low-order

address

FFFE16

FFFC16

FFFA16

FFF816

FFF616

FFF416

FFF216

FFF016

FFEE16

FFEC16

FFEA16

FFE816

FFE616

FFE416

FFE216

FFE016

FFDE16

FFDC16

FFDA16

FFD816

FFD616

FFD416

FFD216

FFD016

FFCE16

Interrupt vector addresses

Table 7.2.1 Interrupt sources and interrupt vector addresses

High-order

address

FFFF16

FFFD16

FFFB16

FFF916

FFF716

FFF516

FFF316

FFF116

FFEF16

FFED16

FFEB16

FFE916

FFE716

FFE516

FFE316

FFE116

FFDF16

FFDD16

FFDB16

FFD916

FFD716

FFD516

FFD316

FFD116

FFCF16

Interrupt source

Reset

Zero division

BRK instruction

____

DBC (Note)

Watchdog timer

____

INT0

____

INT1

____

INT2

Timer A0

Timer A1

Timer A2

Timer A3

Timer A4

Timer B0

Timer B1

Timer B2

UART0 receive

UART0 transmit

UART1 receive

UART1 transmit

A-D conversion

DMA0

DMA1

DMA2

DMA3

____

Note: The DBC interrupt is used exclusively for debugger control.

qMaskable interrupt: An interrupt of which request’s acceptance can be disabled by software.

qNon-maskable interrupt (including Zero division, BRK instruction, Watchdog timer interrupts):

An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their

interrupt control registers and are not affected by the interrupt disable flag (I).

Reference

4. RESET

7700 Family Software

Manual

15. WATCHDOG TIMER

7.10 External interrupts

____

(INTi interrupt)

8. TIMER A

9. TIMER B

11. SERIAL I/O

12. A-D CONVERTER

13. DMA CONTROLLER

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