7721 datasheet(102/577 Pages) RENESAS

102 / 577 page

7721 Group User’s Manual

7–5

INTERRUPTS

7.3 Interrupt control

The maskable interrupts are controlled by the following :

•Interrupt request bit

•Interrupt priority level select bits

•Processor interrupt priority level (IPL)

•Interrupt disable flag (I)

Figure 7.3.1 shows the memory assignment of the interrupt control registers, and Figure 7.3.2 shows their

structures.

}

Assigned to the interrupt control register of each interrupt.

Assigned to the processor status register (PS).

7.3 Interrupt control

Fig. 7.3.1 Memory assignment of interrupt control registers

DMA3 interrupt control register

6F16

UART0 transmit interrupt control register

UART0 receive interrupt control register

UART1 transmit interrupt control register

UART1 receive interrupt control register

Timer A0 interrupt control register

Timer A1 interrupt control register

Timer A2 interrupt control register

Timer A3 interrupt control register

Timer A4 interrupt control register

Timer B0 interrupt control register

Timer B1 interrupt control register

Timer B2 interrupt control register

INT0 interrupt control register

INT1 interrupt control register

INT2 interrupt control register

Address

A-D conversion interrupt control register

7016

7116

7216

7316

7416

7516

7616

7716

7816

7916

7A16

7B16

7C16

7D16

7E16

7F16

DMA2 interrupt control register

6E16

DMA1 interrupt control register

6D16

DMA0 interrupt control register

6C16

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