C167CS-L datasheet(19/81 Pages) INFINEON

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C167CS-4R

C167CS-L

Data Sheet

V2.2, 2001-08

Memory Organization

The memory space of the C167CS is configured in a Von Neumann architecture which

means that code memory, data memory, registers and I/O ports are organized within the

same linear address space which includes 16 MBytes. The entire memory space can be

accessed bytewise or wordwise. Particular portions of the on-chip memory have

additionally been made directly bitaddressable.

The C167CS incorporates 32 KBytes of on-chip mask-programmable ROM (not in the

ROM-less derivative, of course) for code or constant data. The 32 KBytes of the on-chip

ROM can be mapped either to segment 0 or segment 1.

3 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined

variables, for the system stack, general purpose register banks and even for code. A

…, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2

× 512 bytes) of the address space are reserved for the Special Function

used for controlling and monitoring functions of the different on-chip units. Unused SFR

addresses are reserved for future members of the C166 Family.

8 KBytes of on-chip Extension RAM (XRAM), organized as two blocks of 2 KByte and

6 KByte, respectively, are provided to store user data, user stacks, or code. The XRAM

is accessed like external memory and therefore cannot be used for the system stack or

for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with

maximum speed.

In order to meet the needs of designs where more memory is required than is provided

on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the

microcontroller.

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