C167CS-L datasheet(74/81 Pages) INFINEON

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C167CS-4R

C167CS-L

Data Sheet

V2.2, 2001-08

Bus Cycle Control via READY Input

The duration of an external bus cycle can be controlled by the external circuitry via the

READY input signal.

Synchronous READY permits the shortest possible bus cycle but requires the input

signal to be synchronous to the reference signal CLKOUT.

Asynchronous READY puts no timing constraints on the input signal but incurs one

waitstate minimum due to the additional synchronization stage.

Notes (Valid for Table 19 and Figure 21)

1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

2) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may

be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a

demultiplexed bus without MTTC waitstate this delay is zero.

3) These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT,

it must fulfill

tc27 in order to be safely synchronized.

Proper deactivation of READY is guaranteed if READY is deactivated in response to the trailing (rising) edge

of the corresponding command (RD or WR).

4) READY sampled HIGH at this sampling point generates a READY controlled waitstate,

READY sampled LOW at this sampling point terminates the currently running bus cycle.

5) If the next following bus cycle is READY controlled, an active READY signal must be disabled before the first

valid sample point for the next bus cycle. This sample point depends on the MTTC waitstate of the current

cycle, and on the MCTC waitstates and the ALE mode of the next following cycle. If the current cycle uses a

multiplexed bus the intrinsic MUX waitstate adds another CLKOUT cycle to the READY deactivation time.

Table 19

READY Timing (Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit

min.

max.

Input setup time to CLKOUT rising edge

Valid for: READY input

tc25 CC

–

Input hold time after CLKOUT rising edge

Valid for: READY input

tc26 CC

–

Asynchronous READY input low time3)

tc27 CC

tc5 + tc25 –

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