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C167CS-L датащи(PDF) 18 Page - Infineon Technologies AG |
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C167CS-L датащи(HTML) 18 Page - Infineon Technologies AG |
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18 / 81 page ![]() C167CS-4R C167CS-L Data Sheet 14 V2.2, 2001-08 Functional Description The architecture of the C167CS combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. Figure 3 gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C167CS. Note: All time specifications refer to a CPU clock of 40 MHz (see definition in the AC Characteristics section). Figure 3 Block Diagram The program memory, the internal RAM (IRAM) and the set of generic peripherals are connected to the CPU via separate buses. A fourth bus, the XBUS, connects external resources as well as additional on-chip resources, the X-Peripherals (see Figure 3). The XBUS resources (XRAM, CAN) of the C167CS can be individually enabled or disabled during initialization. Register XPERCON selects the required modules which are then enabled by setting the general X-Peripheral enable bit XPEN (SYSCON.2). Modules that are disabled consume neither address space nor port pins. Note: The default value of register XPERCON after reset selects 2 KByte XRAM and module CAN1, so the default XBUS resources are compatible with the C167CR. C166-Core CPU Interrupt Bus XTAL Osc / PLL RTC WDT 32 16 Interrupt Controller 16-Level Priority PEC External Instr. / Data GPT T2 T3 T4 T5 T6 SSC BRGen (SPI) ASC0 BRGen (USART) ADC 10-Bit 16+8 Channels PWM CCOM1 T0 T1 CCOM2 T7 T8 EBC XBUS Control External Bus Control IRAM Internal RAM 3 KByte ProgMem ROM 32 KByte Data Data 16 16 16 CAN1 Rev 2.0B active Instr. / Data Port 0 XRAM 6+2 KByte 8 8 Port 1 16 16 16 Port 5 Port 3 15 Port 7 8 Port 8 8 16 Peripheral Data Bus 16 CAN2 Rev 2.0B active MCB04323_7CS |
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