поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

C167CS-L датащи(PDF) 59 Page - Infineon Technologies AG

номер детали C167CS-L
подробное описание детали  16-Bit Single-Chip Microcontroller
PDF  81 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  INFINEON [Infineon Technologies AG]
домашняя страница  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

C167CS-L датащи(HTML) 59 Page - Infineon Technologies AG

Back Button C167CS-L Datasheet HTML 55Page - Infineon Technologies AG C167CS-L Datasheet HTML 56Page - Infineon Technologies AG C167CS-L Datasheet HTML 57Page - Infineon Technologies AG C167CS-L Datasheet HTML 58Page - Infineon Technologies AG C167CS-L Datasheet HTML 59Page - Infineon Technologies AG C167CS-L Datasheet HTML 60Page - Infineon Technologies AG C167CS-L Datasheet HTML 61Page - Infineon Technologies AG C167CS-L Datasheet HTML 62Page - Infineon Technologies AG C167CS-L Datasheet HTML 63Page - Infineon Technologies AG Next Button
Zoom Inzoom in Zoom Outzoom out
 59 / 81 page
background image
C167CS-4R
C167CS-L
Data Sheet
55
V2.2, 2001-08
AC Characteristics
Definition of Internal Timing
The internal operation of the C167CS is controlled by the internal CPU clock
fCPU. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 11).
Figure 11
Generation Mechanisms for the CPU Clock
The CPU clock signal
fCPU can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
fCPU. This influence must
be regarded when calculating the timings for the C167CS.
Note: The example for PLL operation shown in Figure 11 refers to a PLL factor of 4.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
MCT04338
f
OSC
f
CPU
Phase Locked Loop Operation
TCL
f
OSC
f
CPU
Direct Clock Drive
f
OSC
f
CPU
Prescaler Operation
TCL
TCL
TCL
TCL
TCL



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com