C167CS-L datasheet(36/81 Pages) INFINEON

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C167CS-4R

C167CS-L

Data Sheet

V2.2, 2001-08

CAN-Modules

The integrated CAN-Modules handle the completely autonomous transmission and

reception of CAN frames in accordance with the CAN specification V2.0 part B (active),

i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit

identifiers as well as extended frames with 29-bit identifiers.

The modules provide Full CAN functionality on up to 15 message objects each. Message

object 15 may be configured for Basic CAN functionality. Both modes provide separate

masks for acceptance filtering which allows to accept a number of identifiers in Full CAN

mode and also allows to disregard a number of identifiers in Basic CAN mode. All

message objects can be updated independent from the other objects and are equipped

for the maximum message length of 8 bytes.

The bit timing is derived from the XCLK and is programmable up to a data rate of 1 Mbit/

s. Each CAN-Module uses two pins of Port 4 or Port 8 to interface to an external bus

transceiver. The interface pins are assigned via software.

Module CAN2 is identical with the first one, except that it uses a separate address area

and a separate interrupt node.

The two CAN modules can be internally coupled by assigning their interface pins to the

same two port pins, or they can interface to separate CAN buses.

Note: When any CAN interface is assigned to Port 4, the respective segment address

lines on Port 4 cannot be used. This will limit the external address space.

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been

implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be

disabled in the time interval until the EINIT (end of initialization) instruction has been

executed. Thus, the chip’s start-up procedure is always monitored. The software has to

be designed to service the Watchdog Timer before it overflows. If, due to hardware or

software related failures, the software fails to do so, the Watchdog Timer overflows and

generates an internal hardware reset and pulls the RSTOUT pin low in order to allow

external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/

256. The high byte of the Watchdog Timer register can be set to a prespecified reload

value (stored in WDTREL) in order to allow further variation of the monitored time

interval. Each time it is serviced by the application software, the high byte of the

Watchdog Timer is reloaded. Thus, time intervals between 12.8

µs and 419 ms can be

monitored (@ 40 MHz).

The default Watchdog Timer interval after reset is 3.27 ms (@ 40 MHz).

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