C167CS-L datasheet(67/81 Pages) INFINEON

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C167CS-4R

C167CS-L

Data Sheet

V2.2, 2001-08

AC Characteristics

Figure 16

CLKOUT Signal Timing

Variable Memory Cycles

The bus timing shown below is programmable via the BUSCONx registers. The duration

of ALE and two types of waitstates can be selected. This table summarizes the possible

bus cycle durations.

Table 15

CLKOUT Reference Signal

Parameter

Symbol

Limits

Unit

min.

max.

CLKOUT cycle time

tc5

40/30/251)

1) The CLKOUT cycle time is influenced by the PLL jitter (given values apply to f

CPU = 25/33/40 MHz).

For a single CLKOUT cycle (2 TCL) the deviation caused by the PLL jitter is below 1 ns (for

fCPU > 25 MHz).

For longer periods the relative deviation decreases (see PLL deviation formula).

CLKOUT high time

tc6

CC 8

–

CLKOUT low time

tc7

CC 6

–

CLKOUT rise time

tc8

CC –

4ns

CLKOUT fall time

tc9

CC –

4ns

Table 16

Variable Memory Cycles

Bus Cycle Type

Bus Cycle Duration

Unit 25/33/40 MHz, 0 Waitstates

Demultiplexed bus cycle

with normal ALE

4 + 2

× (15 - <MCTC>)

+ 2

× (1 - <MTTC>)

TCL 80 ns

/ 60.6 ns / 50 ns

Demultiplexed bus cycle

with extended ALE

6 + 2

× (15 - <MCTC>)

+ 2

× (1 - <MTTC>)

TCL 120 ns / 90.9 ns / 75 ns

Multiplexed bus cycle

with normal ALE

6 + 2

× (15 - <MCTC>)

+ 2

× (1 - <MTTC>)

TCL 120 ns / 90.9 ns / 75 ns

Multiplexed bus cycle

with extended ALE

8 + 2

× (15 - <MCTC>)

+ 2

× (1 - <MTTC>)

TCL 160 ns / 121.2 ns / 100 ns

MCT04415

CLKOUT

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