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C167CS-L датащи(PDF) 61 Page - Infineon Technologies AG

номер детали C167CS-L
подробное описание детали  16-Bit Single-Chip Microcontroller
PDF  81 Pages
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производитель  INFINEON [Infineon Technologies AG]
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C167CS-4R
C167CS-L
Data Sheet
57
V2.2, 2001-08
Due to this adaptation to the input clock the frequency of
fCPU is constantly adjusted so
it is locked to
fOSC. The slight variation causes a jitter of fCPU which also effects the
duration of individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and Figure 12).
For a period of
N
× TCL the minimum value is computed using the corresponding
deviation DN:
(
N
× TCL)min = N × TCLNOM - DN; DN [ns] = ±(13.3 + N × 6.3) / fCPU [MHz],
where
N = number of consecutive TCLs and 1
≤ N ≤ 40.
So for a period of 3 TCLs @ 25 MHz (i.e.
N = 3): D3 = (13.3 + 3 × 6.3) / 25 = 1.288 ns,
and (3TCL)min = 3TCLNOM - 1.288 ns = 58.7 ns (@ fCPU = 25 MHz).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 12).
Figure 12
Approximated Maximum Accumulated PLL Jitter
±1
±10
1
5
10
20
D
N
±20
±26.5
ns
±30
40 and 10 MHz
This approximated formula is valid for
1
N
40 MHz.
CPU
f
25 MHz
33 MHz
40
MCD04413B
N
16 MHz
20 MHz
10 MHz
Max. jitter
40 MHz



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