DSP56F826 datasheet(56/60 Pages) FREESCALE

56 / 60 page

56F827 Technical Data, Rev. 12

Freescale Semiconductor

•

Measure the thermal resistance from the junction to where the leads are attached to the case. This definition

is approximately equal to a junction to board thermal resistance.

•

Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case

determined by a thermocouple.

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T

thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so

that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire

is placed flat against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the

interface between the case of the package and the interface material. A clearance slot or hole is normally

required in the heat sink. Minimizing the size of the clearance is important to minimize the change in

thermal performance caused by removing part of the thermal interface to the heat sink. Because of the

experimental difficulties with this technique, many engineers measure the heat sink temperature and then

back-calculate the case temperature using a separate measurement of the thermal resistance of the

interface. From this case temperature, the junction temperature is determined from the junction-to-case

thermal resistance.

5.2 Electrical Design Considerations

Use the following list of considerations to assure correct operation:

•

Provide a low-impedance path from the board power supply to each VDD, VDDIO, and VDDA pin on the

controller, and from the board ground to each VSS,VSSIO, and VSSA (GND) pin.

•

The minimum bypass requirement is to place 0.1

μF capacitors positioned as close as possible to the package

supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the

VDD/VSS pairs, including VDDA/VSSA and VDDIO/VSSIO. Ceramic and tantalum capacitors tend to provide

better performance tolerances.

•

Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD, VDDIO, and

VDDA and VSS, VSSIO, and VSSA (GND) pins are less than 0.5 inch per capacitor lead.

CAUTION

This device contains protective circuitry to guard

against damage due to high static voltage or

electrical fields. However, normal precautions are

advised to avoid application of any voltages higher

than maximum-rated voltages to this high-impedance

circuit. Reliability of operation is enhanced if unused

inputs are tied to an appropriate voltage level.

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