DSP56F826 datasheet(28/60 Pages) FREESCALE

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56F827 Technical Data, Rev. 12

Freescale Semiconductor

Table 3-7 Flash Timing Parameters

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF

Characteristic

Symbol

Min

Typ

Max

Unit

Figure

Program time

Tprog*

–

Figure 3-6

Erase time

Terase*

–

Figure 3-7

Mass erase time

Tme*

100

–

Figure 3-8

Endurance1

1. One cycle is equal to an erase program and read.

ECYC

10,000

20,000

–

cycles

Data Retention1

DRET

–

years

The following parameters should only be used in the Manual Word Programming Mode

PROG/ERASE to NVSTR set

up time

Tnvs*

–5

–

Figure 3-6, Figure 3-7,

Figure 3-8

NVSTR hold time

Tnvh*

–5

–

Figure 3-6, Figure 3-7

NVSTR hold time (mass erase)

Tnvh1*

–100

–

Figure 3-8

NVSTR to program set up time

Tpgs*

–10

–

Figure 3-6,

Recovery time

Trcv*

–1

–

Figure 3-6,

Figure 3-7,Figure 3-8

Cumulative program

HV period2

2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be

programmed twice before next erase.

Thv

–3

–

Figure 3-6,

Program hold time3

3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.

*The Flash interface unit provides registers for the control of these parameters.

Tpgh

––

–

Figure 3-6,

Address/data set up time3

Tads

––

–

Figure 3-6,

Address/data hold time3

Tadh

––

–

Figure 3-6,

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