DSP56F826 datasheet(26/60 Pages) FREESCALE

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56F827 Technical Data, Rev. 12

Freescale Semiconductor

VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD

supply (2.5V) from the voltage generated by the 3.3V VDDIO supply, see Figure 3-3. This keeps VDD from

rising faster than VDDIO.

VDD should not rise so late that a large voltage difference is allowed between the two supplies (2).

Typically, this situation is avoided by using external discrete diodes in series between supplies, as shown

in Figure 3-3. The series diodes forward bias when the difference between VDDIO and VDD reaches

approximately 1.4, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper

operation, the difference between supplies will typically be 0.8V and conduction through the diode chain

reduces to essentially leakage current. During supply sequencing, the following general relationship

should be adhered to:

VDDIO > VDD > (VDDIO - 1.4V)

In practice, VDDA is typically connected directly to VDDIO with some filtering.

Figure 3-3 Example Circuit to Control Supply Sequencing

3.4 AC Electrical Characteristics

Timing waveforms in Section 3.4 are tested using the VIL and VIHlevels specified in the DC Characteristics

table. In Figure 3-4 the levels of VIH and VIL for an input signal are shown.

Figure 3-4 Input Signal Measurement References

Figure 3-5 shows the definitions of the following signal states:

•

Active state, when a bus or signal is driven, and enters a low impedance state

•

Tri-stated, when a bus or signal is placed in a high impedance state

•

Data Valid state, when a signal level has reached VOL or VOH

•

Data Invalid state, when a signal level is in transition between VOL and VOH

3.3V

Regulator

2.5V

Regulator

Supply

VDD

VDDIO, VDDA

VIH

VIL

Fall Time

Input Signal

Note: The midpoint is VIL + (VIH – VIL)/2.

Midpoint1

Low

High

Pulse Width

90%

50%

10%

Rise Time

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