DSP56F826 datasheet(43/60 Pages) FREESCALE

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Synchronous Serial Interface (SSI) Timing

56F827 Technical Data, Rev. 12

Freescale Semiconductor

Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)

Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)

Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)

Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only

connected to it at sampling time. (1pf)

Figure 3-24 Equivalent Analog Input Circuit

3.11 Synchronous Serial Interface (SSI) Timing

2. Measured in 10-90% range.

3. LSB = Least Significant Bit.

4. Guaranteed by characterization.

5. tAIC = 1/fADIC

Table 3-14 SSI Master Mode1 Switching Characteristics

Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL < 50pF, fop = 80MHz

Parameter

Symbol

Min

Typ

Max

Units

STCK frequency

—

102

MHz

STCK period3

tSCKW

100

—

STCK high time

tSCKH

504

——

STCK low time

tSCKL

504

——

Output clock rise/fall time

—

Delay from STCK high to STFS (bl) high - Master5

tTFSBHM

0.1

—

0.5

Delay from STCK high to STFS (wl) high - Master5

tTFSWHM

0.1

—

0.5

Delay from SRCK high to SRFS (bl) high - Master5

tRFSBHM

0.6

—

1.3

Delay from SRCK high to SRFS (wl) high - Master5

tRFSWHM

0.6

—

1.3

Delay from STCK high to STFS (bl) low - Master5

tTFSBLM

-1.0

—

-0.1

ADC analog input

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