DSP56F826 datasheet(36/60 Pages) FREESCALE

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56F827 Technical Data, Rev. 12

Freescale Semiconductor

3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5

Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.

Characteristic

Symbol

Min

Max

Unit

See Figure

RESET Assertion to Address, Data and Control

Signals High Impedance

tRAZ

—21

Figure 3-14

Minimum RESET Assertion Duration2

OMR Bit 6 = 0

OMR Bit 6 = 1

2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:

• After power-on reset

• When recovering from Stop state

tRA

275,000T

128T

—

Figure 3-14

RESET Deassertion to First External Address Output

tRDA

33T

34T

Figure 3-14

Edge-sensitive Interrupt Request Width

tIRW

1.5T

—

Figure 3-15

IRQA, IRQB Assertion to External Data Memory

Access Out Valid, caused by first instruction execution

in the interrupt service routine

tIDM

15T

—

Figure 3-16

IRQA, IRQB Assertion to General Purpose Output

Valid, caused by first instruction execution in the

interrupt service routine

tIG

16T

—

Figure 3-16

IRQA Low to First Valid Interrupt Vector Address Out

recovery from Wait State3

3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not

the minimum required so that the IRQA interrupt is accepted.

tIRI

13T

—

Figure 3-17

IRQA Width Assertion to Recover from Stop State4

4. The interrupt instruction fetch is visible on the pins only in Mode 3.

5. Parameters listed are guaranteed by design.

tIW

—

Figure 3-18

Delay from IRQA Assertion to Fetch of first instruction

(exiting Stop)

OMR Bit 6 = 0

OMR Bit 6 = 1

tIF

—

275,000T

12T

Figure 3-18

Duration for Level Sensitive IRQA Assertion to Cause

the Fetch of First IRQA Interrupt Instruction (exiting

Stop)

OMR Bit 6 = 0

OMR Bit 6 = 1

tIRQ

—

275,000T

12T

Figure 3-19

Delay from Level Sensitive IRQA Assertion to First

Interrupt Vector Address Out Valid (exiting Stop)

OMR Bit 6 = 0

OMR Bit 6 = 1

tII

—

275,000T

12T

Figure 3-19

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