PSD4235G2 datasheet(61/89 Pages) STMICROELECTRONICS

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PSD4235G2

Figure 33. Enable Power-down Flow Chart

Other Power Saving Options. The PSD offers

other reduced power saving options that are inde-

pendent of the Power-down mode. Except for the

SRAM Stand-by and PSD Chip Select Input (CSI,

PD2) features, they are enabled by setting bits in

PMMR0 and PMMR2 (as summarised in Table 23

and Table 24).

PLD Power Management

The power and speed of the PLDs are controlled

by the Turbo bit (bit 3) in PMMR0. By setting the

bit to 1, the Turbo mode is off and the PLDs con-

sume the specified Stand-by current when the in-

puts are not switching for an extended time of

70 ns. The propagation delay time is increased af-

ter the Turbo bit is set to 1 (turned off) when the in-

puts change at a composite frequency of less than

15 MHz. When the Turbo bit is reset to 0 (turned

on), the PLDs run at full power and speed. The

Turbo bit affects the PLD’s DC power, AC power,

and propagation delay. See the AC and DC char-

acteristics tables for PLD timing values (Table 67).

Blocking MCU control signals with the PMMR2 bits

can further reduce PLD AC power consumption.

SRAM Stand-by Mode (Battery Backup). The

PSD supports a battery backup mode in which the

contents of the SRAM are retained in the event of

a power loss. The SRAM has Voltage Stand-by

(VSTBY, PE6) that can be connected to an exter-

nal battery. When VCC becomes lower than VSTBY

then the PSD automatically connects to Voltage

Stand-by (VSTBY, PE6) as a power source to the

SRAM. The SRAM Stand-by current (ISTBY) is typ-

ically 0.5 µA. The SRAM data retention voltage is

2 V minimum. The Battery-on Indicator (VBATON)

can be routed to PE7. This signal indicates when

the VCC has dropped below VSTBY, and that the

SRAM is running on battery power.

PSD Chip Select Input (CSI, PD2)

PD2 of Port D can be configured in PSDsoft Ex-

press as PSD Chip Select Input (CSI). When Low,

the signal selects and enables the internal primary

Flash memory, secondary Flash memory, SRAM,

and I/O blocks for Read or Write operations involv-

ing the PSD. A High on PSD Chip Select Input

(CSI, PD2) disables the primary Flash memory,

secondary Flash memory, and SRAM, and reduc-

es the PSD power consumption. However, the

PLD and I/O signals remain operational when PSD

Chip Select Input (CSI, PD2) is High.

There may be a timing penalty when using PSD

Chip Select Input (CSI, PD2) depending on the

speed grade of the PSD that you are using. See

the timing parameter tSLQV in Table 67.

Input Clock. The PSD provides the option to turn

off CLKIN (PD1) to the PLD to save AC power con-

sumption. CLKIN (PD1) is an input to the PLD

AND Array and the Output Macrocells (OMC).

During Power-down mode, or, if CLKIN (PD1) is

not being used as part of the PLD logic equation,

the clock should be disabled to save AC power.

CLKIN (PD1) is disconnected from the PLD AND

Array or the Macrocells block by setting bits 4 or 5

to a 1 in PMMR0.

Table 50. APD Counter Operation

Enable APD

Set PMMR0 Bit 1 = 1

PSD in Power

Down Mode

ALE/AS idle

for 15 CLKIN

clocks?

RESET

Yes

OPTIONAL

Disable desired inputs to PLD

by setting PMMR0 bits 4 and 5

and PMMR2 bits 0 to 6.

AI04940

APD Enable Bit

ALE PD Polarity

ALE Level

APD Counter

Not Counting

Pulsing

Not Counting

Counting (Generates PDN after 15 Clocks)

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